Setup connections

Setup connections#

A board is connected to the outside word by three type of connection PCIe, JTAG and FTDI. We can have several of them for each type. For example, The PCIe400 card has one PCIE, one JTAG and 3 FTDI connections. In addition a single JTAG connection can serve different branch, for example one for the maX10 and another one for the agilex FPGA.

The interface_ftdi, interface_jtag and interface_pcie, allow all cases to be handled in close conjunction with the Map file.

FTDI connection#

  interface_ftdi:
    j5: 
      interface: FT629ULC
    j9: 
      interface: FT60K5V8
    j11: 
      interface: FT8NUHD2

A board can be connected to several FTDI controllers at the same time. The interface_ftdi is a dictionary that associates a key with the FDTI controller. The key is used in the map in order to link a component to its FTDI chain (column ftdi). Any value can be used to identify a controller and there is no limitation on the number of controller.

interface (str | int)

serial number of the FTDI controller or the number of the USB device linked to the FTDI controller.

JTAG connection#

  interface_jtag:
    agilex: 
      interface: PCIe400
      device: null
      node: -1
      sys_hz: null
      scl_hz: null
    max10:
      interface: PCIe400
      device: 0x031830DD
      node: -1
      sys_hz: null
      scl_hz: null

A JTAG connection serves two independent branch one for the max10 and the second one for Agilex FPGA. The key identifying the branch agilex or max10 is used in the map in order to link a component to its branch (column jtag). Any value can be used to identify a branch and there is no limitation on the number of branch or JTAG connection.

interface (int | str)

identifier of the JTAG cable:

  • The rank of the cable attached to the server, starting from 1.

  • Identifier of the JTAG cable. This is the only member guaranteed to remain across invocations and survive system reboot. It can be found using pcie40_aji command, e.g.: 0x01000001

  • USB port to which JTAG cable is connected, e.g. 1-1.

  • Name of the JTAG cable given by jtagconfig command, e.g. Agilex I-Series SOC Dev Kit

device (int | str)

identifier of the device on the JTAG chain:

  • The rank of the FPGA device in JTAG chain, starting from 0.

  • Hex identifier of the FPGA in JTAG chain. It can be found using pcie40_aji or jtagconfig command, e.g. 0x0343B0DD

  • Name of the FPGA device in JTAG chain, that can be found using pcie40_aji orjtagconfig command. e.g. AGFB027R24C(.|B|R2|R0)/..

node (int | null)

Rank of the node interfacing the JTAG connection to the avalon memory map bus. This is an optional argument starting from 0. The default behavior is to use the first JTAG to AVMM node available in the hierarchy. The value -1 mean not used

sys_hz (int | null)

the system clock frequency of AVMM bus in hertz. By default, it is set to 400 MHz.

scl_hz (int | null)

the I2C clock frequency (SCL) in hertz. By default, it is set to 400 kHz.

PCIe connection#

  interface_pcie:
    ecs:
      interface: 0
      bar: 2

A PCIe interface can serve several bar. The key identifying the bar, ecs, is used in the map in order to link a component to its branch (column pcie). Any value can be used to identify a bar and there is no limitation on the number of bar.

interface (int)

the address of the board on the pcie bus.

bar (int)

address of the PCIe to AVMM controller. For the PCIe400 it is equal to 2.

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